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Abstract 2D layered semiconductors have attracted considerable attention for beyond‐Si complementary metal‐oxide‐semiconductor (CMOS) technologies. They can be prepared into ultrathin channel materials toward ultrascaled device architectures, including double‐gate field‐effect‐transistors (DGFETs). This work presents an experimental analysis of DGFETs constructed from chemical vapor deposition (CVD)‐grown monolayer (1L) molybdenum disulfide (MoS₂) with atomic layer deposition (ALD) of hafnium oxide (HfO₂) high‐k gate dielectrics (top and bottom). This extends beyond previous studies of DGFETs based mostly on exfoliated (few‐nm thick) MoS₂flakes, and advances toward large‐area wafer‐scale processing. Here, significant improvements in performance are obtained with DGFETs (i.e., improvements in ON/OFF ratio, ON‐state current, sub‐threshold swing, etc.) compared to single top‐gate FETs. In addition to multi‐gate device architectures (e.g., DGFETs), the scaling of the equivalent oxide thickness (EOT) is crucial toward improved electrostatics required for next‐generation transistors. However, the impact of EOT scaling on the characteristics of CVD‐grown MoS₂DGFETs remains largely unexplored. Thus, this work studies the impact of EOT scaling on subthreshold swing (SS) and gate hysteresis using current–voltage (I–V) measurements with varying sweep rates. The experimental analysis and results elucidate the basic mechanisms responsible for improvements in CVD‐grown 1L‐MoS₂DGFETs compared to standard top‐gate FETs. 

Abstract Recent studies of resistive switching devices with hexagonal boron nitride (h-BN) as the switching layer have shown the potential of two-dimensional (2D) materials for memory and neuromorphic computing applications. The use of 2D materials allows scaling the resistive switching layer thickness to sub-nanometer dimensions enabling devices to operate with low switching voltages and high programming speeds, offering large improvements in efficiency and performance as well as ultra-dense integration. These characteristics are of interest for the implementation of neuromorphic computing and machine learning hardware based on memristor crossbars. However, existing demonstrations of h-BN memristors focus on single isolated device switching properties and lack attention to fundamental machine learning functions. This paper demonstrates the hardware implementation of dot product operations, a basic analog function ubiquitous in machine learning, using h-BN memristor arrays. Moreover, we demonstrate the hardware implementation of a linear regression algorithm on h-BN memristor arrays. 

Abstract Previous work that studied hexagonal boron nitride (h‐BN) memristor DC resistive‐switching characteristics is extended to include an experimental understanding of their dynamic behavior upon programming or synaptic weight update. The focus is on the temporal resistive switching response to driving stimulus (programming voltage pulses) effecting conductance updates during training in neural network crossbar implementations. Test arrays are fabricated at the wafer level, enabled by the transfer of CVD‐grown few‐layer (8 layer) or multi‐layer (18 layer) h‐BN films. A comprehensive study of their temporal response under various conditions–voltage pulse amplitude, edge rate (pulse rise/fall times), and temperature–provides new insights into the resistive switching process toward optimized devices and improvements in their implementation of artificial neural networks. The h‐BN memristors can achieve multi‐state operation through ultrafast pulsed switching (< 25 ns) with high energy efficiency (≈10 pJ pulse⁻¹).